1) Field of the Invention
This invention relates generally to the fabrication of semiconductor devices and more particularly to the fabrication of a MOS transistor without spacers and using low k materials.
2) Description of the Prior Art
Fabrication of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFET) and complementary metal oxide semiconductor (CMOS) integrated circuits, involves numerous processing steps. Each step may potentially have an adverse effect on one or more device components.
In a typical MOSFET, a source and a drain are formed in an active region of a semiconductor layer by implanting N-type or P-type impurities in a layer of semiconductor material. Disposed between the source and drain is a body region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. It is noted that MOSFETs can be formed in bulk format (for example, the active region being formed in a silicon substrate) or in a semiconductor-on-insulator (SOI) format (for example, in a silicon film that is disposed on a insulating layer that is, in turn, disposed on a silicon substrate).
A pervasive trend in modern integrated circuit manufacture is to produce transistors, and the structural features thereof, that are as small as possible. A factor in device performance is the capacitance of the elements of the circuit. Techniques are need to reduce capacitance.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.
U.S. Pat. No. 6,613,637: Composite spacer scheme with low overlapped parasitic capacitance—Formation of composite spacer in semiconductor device, e.g. metal oxide semiconductor field effect transistor device, by depositing low dielectric constant spacer layer on first spacer layer, and anisotropically etching the combined layers—Inventor: Lee, et al.
US20040171201A1: Low K-gate spacers by fluorine implantation—Fabrication of metal oxide semiconductor field effect transistor device involves performing fluorine implant through silicon nitride etch stop layer and into oxide gate sidewall spacers to form fluorine doped oxide gate sidewall spacers—Inventor: Gambino, Jeffrey P.
U.S. Pat. No. 6,724,051: Nickel silicide process using non-reactive spacer—Inventor: Woo, et al.
U.S. Pat. No. 6,107,667: MOS transistor with low-k spacer to suppress capacitive coupling between gate and source/drain extensions—Fabrication of an ultra large scale integration metal oxide semiconductor field effect transistor, involves providing a low-k spacer to suppress capacitive coupling between gate and source/drain extensions Inventor: An, et al.
US20040262692A1: Nonplanar device with stress incorporation layer and method of fabrication—Inventor: Hareland, et al.
U.S. Pat. No. 6,825,529 Stress inducing spacers—Spacer structure for semiconductor devices formed in substrate, has two spacer structures, each comprising stress inducing material adjacent to both sidewall of one of device's gate terminal and its channel which applies mechanical stress—Inventor: Chidambarrao